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MC14001B Series B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired.
Features http://onsemi.com MARKING DIAGRAMS
14 PDIP-14 P SUFFIX CASE 646 1 14 SOIC-14 D SUFFIX CASE 751A 1 14 TSSOP-14 DT SUFFIX CASE 948G 1 Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C Device MC14001B MC14011B MC14023B MC14025B MC14071B MC14073B MC14081B MC14082B 14 SOEIAJ-14 F SUFFIX CASE 965 1 xx = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) MC140xxB ALYWG 14 0xxB ALYWG G 140xxBG AWLYWW MC140xxBCP AWLYYWWG
* Supply Voltage Range = 3.0 Vdc to 18 Vdc * All Outputs Buffered * Capable of Driving Two Low-power TTL Loads or One Low-power * * *
Schottky TTL Load Over the Rated Temperature Range. Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B Pin-for-Pin Replacements for Corresponding CD4000 Series B Suffix Devices Pb-Free Packages are Available
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering)
DEVICE INFORMATION
Description Quad 2-Input NOR Gate Quad 2-Input NAND Gate Triple 3-Input NAND Gate Triple 3-Input NOR Gate Quad 2-Input OR Gate Triple 3-Input AND Gate Quad 2-Input AND Gate Dual 4-Input AND Gate
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 6
1
Publication Order Number: MC14001B/D
MC14001B Series
LOGIC DIAGRAMS
NOR MC14001B Quad 2-Input NOR Gate
1 2
NAND MC14011B Quad 2-Input NAND Gate
1 2 5 6 8 9 12 13
OR MC14071B Quad 2-Input OR Gate
1 2 5 6 8 9 12 13
AND MC14081B Quad 2-Input AND Gate
1 2 5 6 8 9 12 13
3
3
3
3
2 INPUT
5 6 8 9 12 13
4
4
4
4
10
10
10
10
11
11
11
11
MC14025B Triple 3-Input NOR Gate
1 2 8 3 4 5 11 12 13 9
MC14023B Triple 3-Input NAND Gate
1 2 8 3 4 5 11 12 13 9
MC14073B Triple 3-Input AND Gate
1 2 8 3 4 5 11 12 13 9
MC14082B Dual 4-Input AND Gate
2 3 4 5 9 10 11 12
1
3 INPUT
6
6
6
13 NC = 6, 8
10
10
10
VDD = PIN 14 VSS = PIN 7 FOR ALL DEVICES
PIN ASSIGNMENTS
MC14001B Quad 2-Input NOR Gate
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C
MC14011B Quad 2-Input NAND Gate
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C
MC14023B Triple 3-Input NAND Gate
IN 1A IN 2A IN 1B IN 2B IN 3B OUTB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 3C IN 2C IN 1C OUTC OUTA IN 3A
MC14025B Triple 3-Input NOR Gate
IN 1A IN 2A IN 1B IN 2B IN 3B OUTB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 3C IN 2C IN 1C OUTC OUTA IN 3A
MC14071B Quad 2-Input OR Gate
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C
MC14073B Triple 3-Input AND Gate
IN 1A IN 2A IN 1B IN 2B IN 3B OUTB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 3C IN 2C IN 1C OUTC OUTA IN 3A
MC14081B Quad 2-Input AND Gate
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C
MC14082B Dual 4-Input AND Gate
OUTA IN 1A IN 2A IN 3A IN 4A NC VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD OUTB IN 4B IN 3B IN 2B IN 1B NC
NC = NO CONNECTION
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II II I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIII IIII I I I I IIII I II I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I I I I I I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I III I II II IIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I II III I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIII I I I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII II I IIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I I II IIII I III I I I I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII III IIIII I I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I I I I III II III II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Total Supply Current (3) (4) (Dynamic plus Quiescent, Per Gate, CL = 50 pF)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)
Output Voltage Vin = VDD or 0
(VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)
Vin = 0 or VDD
Characteristic
"0" Level
"1" Level
"1" Level
Source
Sink
Symbol
VOH
VOL
IOH
VIH
IDD
IOL
Cin
VIL
Iin
IT
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
-
MC14001B Series
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- 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 - - - - - - - - - - - - 55_C 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 1.5 3.0 4.0 - - - - - - - - - - - - - - - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 IT = (0.3 mA/kHz) f + IDD/N IT = (0.6 mA/kHz) f + IDD/N IT = (0.9 mA/kHz) f + IDD/N 0.51 1.3 3.4 Min 3.5 7.0 11 - - - - - - - - - - - 0.00001 - 4.2 - 0.88 - 2.25 - 8.8 0.0005 0.0010 0.0015 Typ (2) 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 7.5 1.5 3.0 4.0 - - - - - - - - - - - - - - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 - - - - - - - - - - - 125_C 1.0 0.05 0.05 0.05 Max 7.5 15 30 1.5 3.0 4.0 - - - - - - - - - - - - - - mAdc mAdc mAdc mAdc mAdc Unit Vdc Vdc Vdc Vdc pF
3
MC14001B Series
B-SERIES GATE SWITCHING TIMES
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII I IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I IIIII I IIIII I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I
Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 Min - - - - - - Typ (6) 100 50 40 100 50 40 Max 200 100 80 200 100 80 Unit ns Output Rise Time, All B-Series Gates tTLH = (1.35 ns/pF) CL + 33 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/PF) CL + 20 ns Output Fall Time, All B-Series Gates tTHL = (1.35 ns/pF) CL + 33 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns tTHL ns Propagation Delay Time MC14001B, MC14011B only tPLH, tPHL = (0.90 ns/pF) CL + 80 ns tPLH, tPHL = (0.36 ns/pF) CL + 32 ns tPLH, tPHL = (0.26 ns/pF) CL + 27 ns All Other 2, 3, and 4 Input Gates tPLH, tPHL = (0.90 ns/pF) CL + 115 ns tPLH, tPHL = (0.36 ns/pF) CL + 47 ns tPLH, tPHL = (0.26 ns/pF) CL + 37 ns 8-Input Gates (MC14068B, MC14078B) tPLH, tPHL = (0.90 ns/pF) CL + 155 ns tPLH, tPHL = (0.36 ns/pF) CL + 62 ns tPLH, tPHL = (0.26 ns/pF) CL + 47 ns tPLH, tPHL ns 5.0 10 15 5.0 10 15 5.0 10 15 - - - - - - - - - 125 50 40 160 65 50 200 80 60 250 100 80 300 130 100 350 150 110 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 14 PULSE GENERATOR INPUT OUTPUT * CL OUTPUT INVERTING VDD 20 ns INPUT tPHL 90% 50% 10% tTHL tPLH 90% 50% 10% tTLH tPHL 90% 50% 10% tPLH VOH VOL VOH VOL 20 ns VDD 0V 7 VSS *All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS. OUTPUT NON-INVERTING tTLH tTHL
SWITCHING CHARACTERISTICS (5) (CL = 50 pF, TA = 25_C)
Figure 1. Switching Time Test Circuit and Waveforms
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MC14001B Series
CIRCUIT SCHEMATIC NOR, OR GATES
MC14001B, MC14071B One of Four Gates Shown
VDD 1, 6, 8, 13 * 2, 5, 9, 12 14 VDD
MC14025B One of Three Gates Shown
VDD 1, 3, 11 2, 4, 12 3, 4, 10, 11 * VSS 9, 6, 10 14 VDD
VSS *Inverter omitted in MC14001B
7
VSS VDD
8, 5, 13 7 VSS VSS
*Inverter omitted in MC14025B
CIRCUIT SCHEMATIC NAND, AND GATES
MC14023B, MC14073B One of Three Gates Shown
VDD *
MC14011B, MC14081B One of Four Gates Shown
14 VDD
3, 4, 10, 11 2, 4, 12 1, 3, 11 14 VDD 2, 5, 9, 12 1, 6, 8, 13 * 9, 6, 10 8, 5, 13 7 *Inverter omitted in MC14023B VSS 7 VSS *Inverter omitted in MC14011B
VSS VDD
VSS
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MC14001B Series
TYPICAL B-SERIES GATE CHARACTERISTICS
N-CHANNEL DRAIN CURRENT (SINK)
5.0 - 10 - 9.0 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) 4.0 3.0 TA = - 55C - 40C + 85C + 25C + 125C - 8.0 - 7.0 - 6.0 - 5.0 - 4.0 - 3.0 - 2.0 - 1.0 0 0 1.0 2.0 3.0 4.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 5.0 0 0 - 1.0 - 2.0 - 3.0 - 4.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) - 5.0 + 85C - 40C + 25C TA = - 55C
P-CHANNEL DRAIN CURRENT (SOURCE)
2.0 1.0
+ 125C
Figure 2. VGS = 5.0 Vdc
20 18 ID , DRAIN CURRENT (mA) 16 14 12 10 8.0 6.0 4.0 2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 9.0 10 TA = - 55C - 40C + 25C + 85C + 125C - 50 - 45 ID , DRAIN CURRENT (mA) - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5.0 0 0
Figure 3. VGS = - 5.0 Vdc
TA = - 55C + 25C - 40C + 85C + 125C
- 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 4. VGS = 10 Vdc
50 45 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) 40 35 30 25 20 15 10 5.0 0 0 2.0 4.0 6.0 8.0 10 12 14 16 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 18 20 + 125C TA = - 55C - 40C + 25C + 85C - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 0
Figure 5. VGS = - 10 Vdc
TA = - 55C - 40C + 25C + 85C + 125C
- 2.0 - 4.0 - 6.0 - 8.0 - 10 - 12 - 14 - 16 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
- 18 - 20
Figure 6. VGS = 15 Vdc
Figure 7. VGS = - 15 Vdc
These typical curves are not guarantees, but are design aids. Caution: The maximum rating for output current is 10 mA per pin.
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MC14001B Series
TYPICAL B-SERIES GATE CHARACTERISTICS (cont'd)
VOLTAGE TRANSFER CHARACTERISTICS
V out , OUTPUT VOLTAGE (Vdc)
5.0 4.0 3.0 2.0 1.0 0 0 1.0 2.0
SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR
V out , OUTPUT VOLTAGE (Vdc)
10 8.0 6.0 4.0 2.0 0 0 2.0 4.0
SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND
SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND
3.0 4.0 5.0 Vin, INPUT VOLTAGE (Vdc)
6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc)
Figure 8. VDD = 5.0 Vdc
Figure 9. VDD = 10 Vdc
16 V out , OUTPUT VOLTAGE (Vdc) 14 12 10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range from an ideal "1" or "0" input level which does not produce output state change(s). The typical and guaranteed limit values of the input values VIL and VIH for the output(s) to be at a fixed voltage VO are given in the Electrical Characteristics table. VIL and VIH are presented graphically in Figure 11. Guaranteed minimum noise margins for both the "1" and "0" levels =
1.0 V with a 5.0 V supply 2.0 V with a 10.0 V supply 2.5 V with a 15.0 V supply
Figure 10. VDD = 15 Vdc
Vout VO
VDD
Vout VO
VDD
VO VDD 0 VIL VIH Vin
VO VDD 0 VIL VSS = 0 VOLTS DC VIH Vin
(a) Inverting Function
(b) Non-Inverting Function
Figure 11. DC Noise Immunity
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MC14001B Series
ORDERING INFORMATION
Device MC14001BCP MC14001BCPG MC14001BD MC14001BDG MC14001BDR2 MC14001BDR2G MC14001BDTR2 MC14001BDTR2G MC14001BFEL MC14001BFELG Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 Units / Tape & Reel 55 Units / Rail 25 Units / Rail Shipping
2500 Units / Tape & Reel
MC14011BCP MC14011BCPG MC14011BD MC14011BDG MC14011BDR2 MC14011BDR2G MC14011BDTR2 MC14011BDTR2G MC14011BF MC14011BFG MC14011BFEL MC14011BFELG
PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 Units / Tape & Reel 50 Units / Rail 55 Units / Rail 25 Units / Rail
2500 Units / Tape & Reel
MC14023BCP MC14023BCPG MC14023BD MC14023BDG MC14023BDR2 MC14023BDR2G MC14023BFEL MC14023BFELG
PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 Units / Tape & Reel 2500 Units / Tape & Reel 55 Units / Rail 25 Units / Rail
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MC14001B Series
ORDERING INFORMATION
Device MC14025BCP MC14025BCPG MC14025BD MC14025BDG MC14025BDR2 MC14025BDR2G MC14025BFEL MC14025BFELG Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 Units / Tape & Reel 2500 Units / Tape & Reel 55 Units / Rail 25 Units / Rail Shipping
MC14071BCP MC14071BCPG MC14071BD MC14071BDG MC14071BDR2 MC14071BDR2G MC14071BDT MC14071BDTG MC14071BDTR2 MC14071BDTR2G MC14071BFEL MC14071BFELG
PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* (Pb-Free) TSSOP-14* TSSOP-14* (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 Units / Tape & Reel 2500 Units / Tape & Reel 96 Units per Rail 2500 Units / Tape & Reel 55 Units / Rail 25 Units / Rail
MC14073BCP MC14073BCPG MC14073BD MC14073BDG MC14073BDR2 MC14073BDR2G MC14073BFEL MC14073BFELG
PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 Units / Tape & Reel 2500 Units / Tape & Reel 55 Units / Rail 25 Units / Rail
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MC14001B Series
ORDERING INFORMATION
Device MC14081BCP MC14081BCPG MC14081BD MC14081BDG MC14081BDR2 MC14081BDR2G MC14081BDTR2 MC14081BDTR2G MC14081BFEL MC14081BFELG Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 Units / Tape & Reel 55 Units / Rail 25 Units / Rail Shipping
2500 Units / Tape & Reel
MC14082BCP MC14082BCPG MC14082BD MC14082BDG MC14082BDR2 MC14082BDR2G
PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) 2500 Units / Tape & Reel 55 Units / Rail 2000 Units / Box
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC14001B Series
PACKAGE DIMENSIONS
PDIP-14 CASE 646-06 ISSUE P
14
8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01
A F N -T-
SEATING PLANE
L C
H
G
D 14 PL
K
M
J M
DIM A B C D F G H J K L M N
0.13 (0.005)
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MC14001B Series
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
12
MC14001B Series
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V N
S
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_
SOLDERING FOOTPRINT*
7.06 1
0.36
14X
14X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
13
EEE CCC EEE CCC
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC14001B Series
PACKAGE DIMENSIONS
SOEIAJ-14 CASE 965-01 ISSUE A
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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14
MC14001B/D

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